1. Field of the Invention
The present invention relates to substrate potential generating circuits and semiconductor devices including the same, and particularly to a circuit applying a negative substrate potential to a p-type semiconductor substrate and a semiconductor device including the same.
2. Description of the Background Art
FIG. 10 is a schematic diagram showing one example of a conventional substrate potential generating circuit employed in a dynamic random access memory (DRAM) and the like. Referring to FIG. 10, the substrate potential generating circuit includes an oscillating circuit 30 and a charge pump circuit 40.
Oscillating circuit 30 includes an odd number of inverters 31 connected in series. The output terminal of the last inverter 31 connected to the input terminal of the first inverter 31. Respective inverters 31 are connected to a power supply potential node 10 supplied with a power supply V.sub.CC, and to a ground potential node 20 whose potential is a ground potential. Oscillating circuit 30 is thus constituted of a ring oscillator for providing a clock signal .PHI..sub.cp.
Charge pump circuit 40 includes an inverter 41, capacitors 42 and 43, and p-channel MOS transistors 45, 46 and 47. Inverter 41 receives the clock signal .PHI..sub.cp from oscillating circuit 30 to provide an inverted signal/.PHI..sub.cp of the clock signal .phi..sub.cp. One electrode of capacitor 42 receives the inverted signal/.PHI..sub.cp, and the other electrode thereof is connected to a first node 50. One electrode of capacitor 43 receives the clock signal .PHI..sub.cp, and the other electrode thereof is connected to a second node 44.
p-channel MOS transistor 45 is connected between second node 44 and ground potential node 20, and has its gate electrode connected to ground potential node 20. P-channel MOS transistor 46 is connected between first node 50 and ground potential node 20, and has its gate electrode connected to second node 44. p-channel MOS transistor 47 is connected between first node 50 and the p-type semiconductor substrate, and has its gate electrode connected to first node 50. Specifically, p-channel MOS transistor 47 is diode-connected, so as to allow conduction between first node 50 and the semiconductor substrate when a potential N.sub.1 of first node 50 is lower than a substrate potential V.sub.BB of the semiconductor substrate by an absolute value V.sub.th, or more, of the threshold voltage.
Charge pump circuit 40 thus receives the clock signal .PHI..sub.cp from oscillating circuit 30 to provide first node 50 with a prescribed negative potential, drawing off charges in the semiconductor substrate.
FIG. 11 is a cross sectional view showing a part of a semiconductor substrate on a main surface of which such a substrate potential generating circuit is formed. Referring to FIG. 11, the substrate potential generating circuit includes a p-type semiconductor substrate 50, an N-well 51, a P-well 52, an element isolation region 53, a source/drain 54, a backgate electrode 55, and a gate electrode 56.
N-well 51 is formed by implanting a donor, such as phosphorus, in p-type semiconductor substrate 50. P-well 52 is formed by implanting an acceptor, such as boron, in p-type semiconductor substrate 50. Element isolation region 53 formed of a thick oxide film isolates adjacent elements. Source/drain 54 is formed by implanting an acceptor, such as boron, in N-well 51. Back gate electrode 55 for applying a backgate potential to N-well 51 is formed by implanting a donor, such as arsenic, in N-well 51.
The operation of the substrate potential generating circuit will now be described with reference to FIG. 12.
Referring to FIG. 12(a), oscillating circuit 30 provides a clock signal .PHI..sub.cp changing periodically between an H level (a power supply potential V.sub.CC) and an L level (a ground potential GND). A substrate potential V.sub.BB of the semiconductor substrate is assumed to be approximately the ground potential at a timing t.sub.0 when the clock signal .PHI..sub.cp rises from an L level to an H level.
When the clock signal .PHI..sub.cp rises from an L level to an H level at the timing t.sub.0, a potential N.sub.2 of second node 44 rises, as shown in FIG. 12(d), by capacitive coupling of capacitor 43 receiving the clock signal .phi..sub.cp. When the potential N.sub.2 of second node 44 exceeds an absolute value V.sub.th1 of the threshold voltage of p-channel MOS transistor 45, however, p-channel MOS transistor 45 is rendered conductive. Accordingly, second node 44 and ground potential node 20 conduct, so that the potential N.sub.2 of second node 44 is the absolute value V.sub.th1 of the threshold voltage of p-channel MOS transistor 45. As a result, p-channel MOS transistor 46, the gate electrode of which receives the potential N.sub.2 of second node 44 is rendered non-conductive.
As shown in FIG. 12(b), inverter 41 receives the clock signal .PHI..sub.cp from oscillating circuit 30 to provide an inverted signal/.PHI..sub.cp. When the inverted signal/.PHI..sub.cp falls from an H level to an L level at the time t.sub.0, a potential N.sub.1 of first node 50 drops to a negative potential -k.sub.1 V.sub.CC, as shown in FIG. 12(c), by capacitive coupling of capacitor 42 receiving the inverted signal/.PHI..sub.cp. Here, k.sub.1 is a coupling efficiency between capacitor 42 and first node 50.
When the potential N.sub.1 of first node 50 attains k.sub.1 V.sub.CC, p-channel MOS transistor 47 is rendered conductive, allowing conduction between first node 50 and the semiconductor substrate, so that charges move from the semiconductor substrate to first node 50. The substrate potential V.sub.BB of the semiconductor substrate slightly drops from the ground potential GND, as shown in FIG. 12(e), because of the large capacity of the substrate. The potential N.sub.1 of first node greatly rises from -k.sub.1 V.sub.CC compared with the potential V.sub.BB, as shown in FIG. 12(c), because of the small capacity of node 50. When the potential N.sub.1 of first node 50 is lower than the substrate potential V.sub.BB by an absolute value V.sub.th2 of the threshold voltage of p-channel MOS transistor 47, p-channel MOS transistor 47 is rendered non-conductive.
As shown in FIG. 12(a), when the clock signal .PHI..sub.cp from oscillating circuit 30 falls from an H level to an L level at a timing t.sub.1, the potential N.sub.2 of second node 44 begins to drop from the potential V.sub.th1, as shown in FIG. 12(d), by capacitive coupling of capacitor 43 receiving the clock signal .PHI..sub.cp, rendering p-channel MOS transistor 45 non-conductive. The potential N.sub.2 of second node 44 attains (-kV.sub.CC +V.sub.th1), so that p-channel MOS transistor 46 whose gate receives the potential N.sub.2 of second node 44 is rendered conductive. When p-channel MOS transistor 46 is rendered conductive, first node 50 and ground potential node 20 conduct, so that the potential N.sub.1 of first node 50 attains the ground potential GND, as shown in FIG. 12(c), and p-channel MOS transistor 47 is held non-conductive.
As shown in FIG. 12(b), the inverted signal/.PHI..sub.cp provided from inverter 41 rises from an L level to an H level at the timing t.sub.1. However, the potential N.sub.1 of first node 50 will not rise by capacitive coupling of capacitor 42, since p-channel MOS transistor 46 is in the conductive state, allowing conduction between first node 50 and ground potential node 20.
As shown in FIG. 12(a), when the clock signal .PHI..sub.cp rises from an L level to an H level again at a timing t.sub.2, the potential N.sub.2 of second node 44 rises from the potential (-k.sub.2 V.sub.CC +V.sub.th1), as shown in FIG. 12(d), by capacitive coupling of capacitor 43 receiving the clock signal .PHI..sub.cp. However, when the potential N.sub.2 of second node 44 exceeds the absolute value V.sub.th1 of the threshold voltage of p-channel MOS transistor 45, p-channel MOS transistor 45 is rendered conductive, allowing conduction between second node 44 and ground potential node 20. Accordingly, the potential N.sub.2 of second node 44 is the absolute value V.sub.th1 of the threshold voltage of p-channel MOS transistor 45, so that p-channel MOS transistor 46 whose gate receives the potential N.sub.2 of second node 44 is rendered no-conductive.
As shown in FIG. 12(b), when the inverted signal/.PHI..sub.cp falls from an H level to L level at the timing t.sub.2, the potential N.sub.1 of first node 50 drops to the negative potential -k.sub.1 V.sub.CC, as shown in FIG. 12(c), by capacitive coupling of capacitor 42 receiving the inverted signal/.PHI..sub.cp, rendering p-channel MOS transistor 47 conductive. This allows conduction between first node 50 and the semiconductor substrate, whereby charges move from the semiconductor substrate to first node 50. The substrate potential V.sub.BB of the semiconductor substrate slightly drops from the potential at that time, as shown in FIG. 12(e), because of the large capacity of the substrate. The potential N.sub.1 of first node 50 greatly rises, as shown in FIG. 12(c), because of the small capacity of the node, and when the potential N.sub.1 attains a potential lower than the substrate potential V.sub.BB by the absolute value V.sub.th2 of the threshold voltage of p-channel MOS transistor 47, p-channel MOS transistor 47 is rendered non-conductive.
As described above, the substrate potential V.sub.BB of the semiconductor substrate drops for each rise of the clock signal .PHI..sub.cp from oscillating circuit 30 from an L level to an H level, to finally attain (-k.sub.1 V.sub.CC +V.sub.th2).
However, the absolute value V.sub.th2 of the threshold voltage of p-channel MOS transistor 47, when its gate width is 0.5 .mu.m, for example, will be 1.7V, considering a backgate effect. Since the absolute value V.sub.th2 of the threshold voltage of p-channel MOS transistor 47 attains a large value over 1V, the problem of insufficient decrease of the substrate potential V.sub.BB arises.
Generally, the level required as the substrate potential V.sub.BB is not defined to a single value, varying depending on the kind of the device. Accordingly, a substrate potential generating circuit capable of wide selection of the substrate potential V.sub.BB is desirable.
Specifically, when the power supply potential V.sub.CC is low, for example, 3.3V, the substrate potential V.sub.BB is no more than -1.6V (=-3.3+1.7), assuming that coupling efficiency k.sub.2 is approximately "1". Therefore, where -1.5V is required as the substrate potential V.sub.BB, the substrate potential (-1.5V) approximates to the substrate potential V.sub.BB (-1.6V) obtained by the conventional substrate potential generating circuit, thus approximates to the limit of its capability. Accordingly, in the case of a sub-leak current, it may be difficult even to ensure the potential of -1.6V. In the conventional substrate potential generating circuit, effects of the absolute value V.sub.th2 of the threshold voltage of p-channel MOS transistor 47 cannot be ignored, as the power supply potential V.sub.CC decreases.
In order to make the substrate potential V.sub.BB lower, the H level of the clock signal .PHI..sub.cp can be considered to be made higher than the power supply potential V.sub.CC. In this case, however, a potential difference {(1+k.sub.2) V.sub.CC -V.sub.th1 } is applied as stress between gate electrode 56 of p-channel MOS transistor 46 and N-well 51, as well as a potential difference {(1+k.sub.1) V.sub.CC -V.sub.th2 } is applied as stress between source electrode 54 connected to semiconductor substrate 50 of p-channel MOS transistor 47 and N-well 51, causing adverse effects on the reliability of each element.